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HY57V281620A
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require
low power consumption and extended temperature range . HY57V281620A is organized as 4banks of 2,097,152x16 H Y 5 7 V 2 8 1 6 2 0 A i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y n ch r o nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d b y a s i n g l e c o n t r o l c o m m a n d ( B u r s t l e n g t h o f 1 , 2 , 4 , 8 , o r f u l l p a g e ) , a n d t h e b u r s t c o u n t s e q u e n c e ( s e q u e n t i a l o r i n t e r l e a v e ) . A bu r s t o f r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * Single 3.30.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch - 1, 2, 4, 8 or Full page for Sequential Burst * All inputs and outputs referenced to positive edge of system clock * * Data mask function by UDQM or LDQM Internal four banks operation * - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HY57V281620AT-KI HY57V281620AT-HI HY57V281620AT-PI HY57V281620AT-SI HY57V281620ALT-KI HY57V281620ALT-HI HY57V281620ALT-PI HY57V281620ALT-SI
Clock Frequency
133MHz 133MHz
Power
Organization
Interface
Package
Normal 100MHz 100MHz 133MHz 133MHz Low Power 100MHz 100MHz 4Banks x 2Mbits x16
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Apr.01
HY57V281620A
PIN CONFIGURATION
V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 V DD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54pin TSOP II 400mil x 875mil 0.8mm pin pitch 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA0, BA1
Bank Address
A0 ~ A11
Address
Row Address Strobe, ColR A S , C A S, W E umn Address Strobe, Write Enable UDQM, LDQM DQ0 ~ DQ15 V D D /V S S V D D Q /V S S Q NC Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection
R A S , C A S and W E define the operation Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
Rev. 0.4/Apr.01
2
HY57V281620A
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row counter
CLK
Row active
2M x 1 6 B a n k 3 Row Pre Decoders 2M x 1 6 B a n k 2
X decoders
CKE
2Mx16 Bank 1
X decoders
CS
2Mx16 Bank 0
State Machine
X decoders
RAS
DQ0 DQ1
Sense AMP & I/O Gate
X decoders
I/O Buffer & Logic
CAS
refresh
Memory Cell Array
WE
Column Active
UDQM
Column Pre Decoders Y decoders
DQ14 DQ15
LDQM
Bank Select
Column Add Counter
A0 A1
Address Registers
Address buffers
Burst Counter
A11 BA0 BA1
CAS Latency
Mode Registers
Data Out Control
Pipe Line Control
Rev. 0.4/Apr.01
3
HY57V281620A
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to V S S Voltage on V D D relative to V S S Short Circuit Output Current Power Dissipation Soldering Temperature T i m e TA TS T G V IN, V O U T VDD, VD D Q IO S PD TSOLDER Symbol -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C S e c Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
Parameter Power Supply Voltage Input High voltage Input Low voltage Symbol VD D , VDDQ V IH V IL
(T A = - 4 0 t o 8 5 C )
Min 3.0 2.0 -0.3
Typ 3.3 3.0 0
Max 3.6 V DDQ + 0.3 0.8
Unit V V V
Note 1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0 V 2.V IH( m a x ) i s a c c e p t a b l e 5 . 6 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n . 3 . V I L( m i n ) i s a c c e p t a b l e - 2 . 0 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n .
A C O P E R A T I N G T E S T C O N D I T I O N (TA =
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
- 4 0 t o 8 5 C , V D D = 3 . 3 0 . 3 V , V S S = 0 V )
Symbol V IH / V IL Vtrip tR / tF Voutref CL
Value 2.4/0.4 1.4 1 1.4 50
Unit V V ns V pF
Note
1
Note : 1 . O u t p u t l o a d t o m e a s u r e a c c e s s t i m e s i s e q u i v a l e n t t o t w o T T L g a t e s a n d o n e c a p a c i t o r ( 5 0 p F ) . F o r d e t a i l s , r e f e r t o A C / D C o u t p ut load circuit
Rev. 0.4/Apr.01
4
HY57V281620A
CAPACITANCE
( T A = 2 5C , f = 1 M H z )
-HI Parameter Pin Symbol Min Input capacitance CLK A0 ~ A11, BA0, BA1, CKE, C S, RAS, CAS , W E, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 C I/O 4.0 6.5 4.0 C I1 CI 2 2.5 2.5 Max 3.5 3.8 Min 2.5 2.5
-SI Unit Max 4.0 5.0 pF pF
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output
50pF
50 pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage IL I IL O VOH VOL
( T A = - 4 0 t o 8 5 C , V D D = 3 . 3 0 . 3 V )
Symbol
Min. -1 -1 2.4 -
Max 1 1 0.4
Unit uA uA V V
Note 1 2 IO H = - 4 m A IO L = + 4 m A
Note : 1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V 2.DO U T is disabled, V O U T =0 to 3.6
Rev. 0.4/Apr.01
5
HY57V281620A
DC CHARACTERISTICS II
( T A = - 4 0 t o 8 5 C , V DD =3.3 0.3V, V S S = 0 V )
Speed Parameter Symbol Test Condition -KI Burst length=1, One bank active tR C tR C ( m i n ) , I O L = 0 m A C K E V IL ( m a x ) , t C K = 1 5 n s C K E V IL ( m a x ) , t C K = -HI -PI -SI Unit Note
Operating Current
ID D 1
120
110
100
100
mA
1
Precharge Standby Current in Power Down Mode
ID D 2 P ID D 2 P S
2 mA 2
C K E V IH ( m i n ) , C S V I H ( m i n ) , t C K = 1 5 n s ID D 2 N Precharge Standby Current in Non Power Down Mode ID D 2 N S C K E V IH ( m i n ) , t C K = Input signals are changed one time during 2 c l k s . A l l o t h e r p i n s V D D - 0 . 2 V o r 0.2V 20 mA 10
Input signals are stable. ID D 3 P ID D 3 P S C K E V IL ( m a x ) , t C K = 1 5 n s C K E V IL ( m a x ) , t C K = 7 mA 7
Active Standby Current in Power Down Mode
C K E V IH ( m i n ) , C S V I H ( m i n ) , t C K = 1 5 n s ID D 3 N Active Standby Current in Non Power Down Mode ID D 3 N S C K E V IH ( m i n ) , t C K = Input signals are changed one time during 2 c l k s . A l l o t h e r p i n s V D D - 0 . 2 V o r 0.2V 40 mA 40
Input signals are stable. CL=3 CL=2 120 120 240 120 100 220
Burst Mode Operating Current
ID D 4
tC K tC K ( m i n ) , IO L = 0 m A All banks active tR R C tR R C ( m i n ) , A l l b a n k s a c t i v e
100 100 200 2
100 mA 90 200 mA mA uA 2 3 4 1
Auto Refresh Current
ID D 5
Self Refresh Current
ID D 6
C K E 0.2V 800
Note:
1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II 3.HY57V281620AT-KI/HI/PI/SI 4.HY57V281620ALT-KI/HI/PI/SI
Rev. 0.4/Apr.01
6
HY57V281620A
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-KI Parameter Symbol Min C A S Latency = 3 C A S Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 7.5 1000 7.5 2.5 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 5.4 5.4 5.4 10 2.5 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 3 Max Min 7.5
-HI Max Min 10 1000 10 5.4 6 5.4 6 3 3 2.5 2 1 2 1 2 1 2 1 1 3 3
-PI Max Min 10 1000 12 6 6 6 6 3 3 2.5 2 1 2 1 2 1 2 1 1 3 3
-SI Unit Max ns 1000 ns 6 6 6 6 ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Note
System Clock Cycle Time
Clock High Pulse Width Clock Low Pulse Width C A S Latency = 3 C A S Latency = 2
Access Time From Clock
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time C A S Latency = 3 C A S Latency = 2
CLK to Data Output in High-Z Time
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.4/Apr.01
7
HY57V281620A
AC CHARACTERISTICS II
-KI Parameter Symbol Min Operation R A S Cycle Time Auto Refresh R A S to C A S Delay R A S Active Time RAS Precharge Time R A S to R A S Bank Active Delay C A S to C A S Delay Write Command to Data-In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command C A S Latency = 3 C A S Latency = 2 tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 60 15 45 15 15 1 0 2 4 2 0 2 3 2 1 1 100K 64 65 20 45 20 15 1 0 2 5 2 0 2 3 2 1 1 tRC 60 Max Min 65
-HI Max 100K 64 Min 70 70 20 50 20 20 1 0 2 3 2 0 2 3 2 1 1 -
-PI Max 100K 64 Min 70 70 20 50 20 20 1 0 2 4 2 0 2 3 2 1 1 -
-SI Unit Max 100K 64 ns ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 Note
Precharge to Data Output Hi-Z
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.4/Apr.01
8
HY57V281620A
DEVICE OPERATING OPTION TABLE
HY57V281620A(L)T-KI
C A S Latency 133MHz(7.5ns) 100MHz(10ns) 2CLKs 2CLKs tRCD 2CLKs 2CLKs tRAS 6CLKs 5CLKs tRC 8CLKs 7CLKs tRP 2CLKs 2CLKs tAC 5.4ns 6ns tOH 2.5ns 2.5ns
HY57V281620A(L)T-HI
C A S Latency 133MHz(7.5ns) 100MHz(10ns) 3CLKs 3CLKs tRCD 3CLKs 3CLKs tRAS 6CLKs 6CLKs tRC 9CLKs 9CLKs tRP 3CLKs 3CLKs tAC 5.4ns 6ns tOH 2.5ns 2.5ns
HY57V281620A(L)T-PI
C A S Latency 100MHz(10ns) 83MHz(12ns) 2CLKs 2CLKs tRCD 2CLKs 2CLKs tRAS 5CLKs 5CLKs tRC 7CLKs 7CLKs tRP 2CLKs 2CLKs tAC 6ns 6ns tOH 2.5ns 2.5ns
HY57V281620A(L)T-SI
C A S Latency 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs tRCD 2CLKs 2CLKs tRAS 5CLKs 5CLKs tRC 7CLKs 7CLKs tRP 2CLKs 2CLKs tAC 6ns 6ns tOH 2.5ns 3ns
Rev. 0.4/Apr.01
9
HY57V281620A
COMMAND TRUTH TABLE
A10/ AP OP code
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
BA
Note
Mode Register Set
H
X
L H
L X H L
L X H H
L X
X
No Operation
H
X L H H
X
X
Bank Active Read
H
X
L
X
RA L
V
H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Entry Self Refresh1 Exit L H H H H
X
L
H
L
H
X
CA H L
V
X
L
H
L
L
X
CA H H
V
X V
X
L
L
H
L
X
X L
X
L
H X
H
L
X V
X X X
H L
L L H
L L X H X H X H X V X
L L X H X H X H X V
H H X
X X
X X
H L H H X
Entry Precharge power down Exit
H
L L H H
X X X X L H H X X L V X X
L
H
Clock Suspend
Entry
H
L
Exit
L
H
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2 . X = D o n t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , Opcode = Operand Code, NOP = No Operation
Rev. 0.4/Apr.01
10
HY57V281620A
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 0.4/Apr.01
11

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